The memory cell array of an integrated semiconductor memory, for example a DRAM (e.g., dynamic random access memory) semiconductor memory, contains storage capacitors connected to a bit line via a controllable path of a selection transistor. The selection transistor can be turned off or switched to the on state by applying a control signal to a control terminal. In order to write an information item to one of the memory cells of the memory cell array, the selection transistor of the respective memory cell is switched into the on state and the storage capacitor is charged to a predefined charge by the application of a write voltage to the bit line. The charge stored in the storage capacitor in this case corresponds to the information item to be stored. In this case, a high charge level corresponds to a logic state “1” (high state). A low charge level corresponds to a logic state “0” (low state). Once the information item has been stored in the memory cell, the selection transistor is turned off again. Afterward, the bit lines are precharged to a common potential during a precharge process.
Such a precharge process likewise takes place prior to read-out. In the precharge phase, the bit line and a reference bit line are precharged to a common equalization potential. The precharge can be carried out automatically as a so-called auto-precharge. After the end of the precharge phase, the selection transistor of the memory cell is switched into the on state once again, so that the charge stored on the storage capacitor alters the potential of the bit line. The potential on the bit line is subsequently compared with the potential on the reference bit line in a sense amplifier. Depending on the information item stored in the memory cell, the sense amplifier generates an output signal corresponding to the logic state “0” or to the logic state “1”. Important parameters that characterize the write and read processes are the so-called write and precharge times. The write time is defined by the temporal interval between the instant at which the data are written to the memory cell array and the instant at which the selection transistor connected with the respective memory cell is turned off. The precharge time denotes the subsequent time interval between the instant at which the selection transistor is turned off and the instant at which the selection transistor is switched into the conductive state once again. The write and precharge times will be explained in greater detail with the aid of the signal state diagram illustrated in FIG. 1.
FIG. 1 illustrates a signal state diagram of an integrated DRAM semiconductor memory during a write process with subsequent auto-precharge. The first signal line illustrates the temporal profile of a clock signal CLK. In the normal operating state of the integrated semiconductor memory, the synchronous operating state, command signals CMD are each applied to the integrated semiconductor memory upon the rising and falling signal edges. In the command signal line, the illustration shows an activation signal ACT, a write signal W and a signal NOP, in the case of which no command is prescribed for the integrated semiconductor memory externally. An externally applied data set DQE is illustrated in the third signal line. The fourth signal line illustrates the associated, for example time-delayed, internal data set DQI that is read into one of the memory cells. The fifth signal line shows the profile of an internal control signal IS. The selection transistor is turned on upon a rising signal edge of the internal control signal and the selection transistor is turned off upon a falling signal edge of the internal control signal.
As can be gathered from the signal state diagram, the selection transistor of a selected memory cell is turned on after activation of the integrated semiconductor memory by the activation signal ACT by means of the state change of the internal control signal IS at the instant T1 from the low state to the high state. At the instant T2, the integrated semiconductor memory is driven by a write command W. At the instant T3, a data set D is applied to the data input of the integrated semiconductor memory. At the instant T4, said data set is read as internal data set into the selected memory cell. After the write time tiWR has elapsed, the selection transistor of the memory cell is turned off again at the instant T5 as a result of a signal state change of the internal control signal IS from the high state to the low state. In the case of an automatic precharge of the bit and reference bit lines, the precharge phase begins at the same instant. After the precharge time tiRP has elapsed, the selection transistor is switched into the on state again at the instant T6 in order, by way of example, to read out the information previously read into the memory cell.
The write and precharge times required for a successful write and read process are essentially determined by the design specifications and the technological processes. Precise knowledge of the write and precharge times therefore plays a significant part in the optimization of design and technological processes. Furthermore, the necessary write and precharge times, during the fabrication of the integrated semiconductor memory, give a first indication of whether memory cell elements are defective. If it is possible for the write and read times to be tested as early as at the wafer level, defective memory cells can still be replaced by redundant memory cell elements. Conventional wafer checking tests do not use a dedicated test mode for testing the write and precharge times of an integrated semiconductor memory. The two time parameters can be tested by the application of a write and read signal only to a limited extent. Joint testing of the two time parameters is not possible with present-day test systems. Furthermore, the access speed of semiconductor memories, which becomes faster and faster from generation to generation, presents the test systems with ever greater difficulties in accurate testing.